Design and Performance Analysis of Inexact-Speculative Han Carlson Adder

Abstract

Low power and high speed design is one of the important building blocks in digital circuits. In conventional inexact speculative adder based on Carry look-ahead adder to consume more power issues and longest critical path delay. In this paper, Han Carlson adder based design of the proposed ISA architecture which is fine grain pipelined because to increase the processing speed and reduces the complexity, silicon area and power consumption. Additionally this architecture has been clock gated giving rise to dynamic power reduction opportunity. Functional verification and synthesis of suggested ISA is carried out on 45 nm CMOS technology by using Tanner EDA tool.