Optimization of dual threshold MOSFET for 1-bit full adder cell

Abstract

Power and delay is very important issue in low voltage and low-power application. In most of the digital circuit systems adder are in the critical path that affects the overall speed of the system. In this paper proposes a 10 transistor low power full adder cell with least NMOS and PMOS transistor count that helps to reduce the threshold loss problem. It increases the speed. By using Dual Threshold techniques to improve the threshold loss problem and reduces power consumption compare with other types of adders. Normally full adders need more area but the proposed circuits have negligible area. The threshold techniques are used for good voltage swing. BSIMv13.0 90 nm standard models are used for simulations on Tanner EDA tools.