NANDHINI, S.R; RAJA NANDHINI, J; GAVASKAR, K; INDHUMATHI, R. Optimization of dual threshold MOSFET for 1-bit full adder cell. International Journal of Modern Computation, Information and Communication Technology, [S. l.], v. 3, n. 11 & 12, p. 85–92, 2020. DOI: 10.65000/13sdjx98. Disponível em: https://gjpublications.com/index.php/IJMCICT/article/view/60. Acesso em: 22 oct. 2025.