An Efficient Approach for Design of Low Power Split Radix FFT Processor with Reduced Computational Complexity

Abstract

The purpose of Fast Fourier Transform (FFT) is to compute the frequency domain sequence from its time domain sequence. The Fast Fourier Transform is improved version of Discrete Fourier Transform (DFT), which used to perform the computations faster than DFT approach. Our proposed technique has modified architecture of FFT processor in such a way that it has least number of arithmetic operations to perform the same computation. Whenever dealing with FFT algorithms, the address generation schemes need to be done for both input data and twiddle factors. In this approach the multipliers are enabled whenever necessary, which reduces the dynamic power consumption. Generally the number of arithmetic operations such as multiplications and additions decides the computational complexity of the algorithm. In this approach the numbers of complex multiplications are significantly reduced as compared to Radix-2 FFT algorithm. Similarly the number of used flipflops, Look Up Tables, slices and memory are reduced comparing with previous design. Hence the proposed architecture consumes less dynamic power, have reduced number of multiplications and area efficient.