An Efficient Approach for Test Pattern Generation in Scan Based BIST

Abstract

A new low-power (LP) scan-based BIST technique is proposed based on weighted pseudo random test pattern generation and reseeding. This project describes a LP (low power) Weighted pseudo random test pattern generator (PRPG) which has the capacity to produce the pseudo random test pattern generator with reseeding. LP (low- power) reseeding techniques are used to create a feedback for high accuracy and also cover a number of test vectors. In both techniques, only a small number of flip flops can activate. The gating technique is used to disable unwanted flipflops .Due to low switching activity, power will be minimized. The LFSR is used to implement the test pattern for detecting faults. DFT architecture is used to implement the deterministic BIST for reduced test vectors.The design has been coded in verilog. The simulation results have been viewed by Modelsim software and Quartus II software. The obtained simulation results can be used for industrial applications.