Design and Performance Analysis of VLSI Architecture for Inexact Speculative Adder

Abstract

Low power and high speed design is one of the important building blocks in digital circuits. In conventional Inexact speculative adder based on x-bit adder to consume more power issues and long critical path delay. In this paper, carry look-ahead adder based design of the proposed ISA architecture which is fine grain pipelined because to increase the processing speed. Additionally this architecture has been clock gated giving rise to dynamic power reduction opportunity. Functional verification and hardware implementation of suggested Inexact Speculative Adder (ISA) is carried out on Field Programmable Gate Array (FPGA).